1. Field of the Invention
The present invention relates to a line interface for a high-speed line and, more particularly, to a line interface applicable to the high-speed side of multiplex equipment which is included in a data transmission system.
2. Description of the Prior Art
In a data transmission system, multiplex equipment converts data to be transmitted over a plurality of low-speed lines and data to be transmitted over a plurality of high-speed lines to each other. Data coming in over each low-speed line is received by a particular low-speed line interface assigned to the low-speed line and applied to a multiplex-demultiplex circuit. The data applied to the multiplex-demultiplex circuit from the respective low-speed line interfaces are rearranged and sent out to high-speed lines by high-speed line interfaces each being associated with respective one of the high-speed lines. On the other hand, data received by the high-speed line interfaces and fed to the multiplex-demultiplex circuit are rearranged and sent out to the low-speed lines by the low-speed line interfaces each being associated with respective one of the low-speed lines.
The high-speed line interfaces each receives data to be transmitted to corresponding one of the high-speed lines from the multiplex-demultiplex circuit, multiplexes a transmission frame synchronizing (sync) signal with the data, and then sends the multiplexed signal to be transmitted to the high-speed line. When the high-speed line interface receives a multiplexed signal of received data and reception frame sync signal from corresponding one of the high-speed lines, it removes the frame sync signal from the received signal and transfers the received data to the multiplex-demultiplex circuit.
To remove the reception frame sync signal from the received signal, timing information of the sync signal is essential. The high-speed line interface obtains such timing signal by a frame sync circuit frame-synchronous to received signals incorporated therein. The frame sync circuit also functions to detect errors on the associated high-speed line by monitoring received signals. Specifically, when the frame sync circuit cannot set up frame synchronization to a received signal, it generates a frame error signal to report an error occurred on the high-speed line. The frame error signal is used as a trigger for replacing the defective high-speed line and the high-speed line interface associated therewith with a standby high-speed line and a standby high-speed line interface.
The problem with the conventional high-speed line interface is that it lacks a function of detecting errors occurred in itself. It is likely, therefore, that the conventional high-speed line interface is prevented from being accurately replaced with a stand-by interface when an error occurs therein.